Difference between revisions of "AVR timer interrupts"
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;OCRxA: (output compare register). As soon as the timer reaches a value that is in this register, the appropriate bit in [[#TIFR|TIFR]] is set. This bit is set if the timer runs in ''CTC''-mode, which can be switched on by setting WGMx0-WGMx3 to '''0100''' (setting WGMx2 to 1). | ;OCRxA: (output compare register). As soon as the timer reaches a value that is in this register, the appropriate bit in [[#TIFR|TIFR]] is set. This bit is set if the timer runs in ''CTC''-mode, which can be switched on by setting WGMx0-WGMx3 to '''0100''' (setting WGMx2 to 1). | ||
| + | |||
| + | ;TIMSK; Set the appropriate bit (OCIExA) to enable timer interrupts. | ||
| + | |||
| + | ==Interrupt vector== | ||
| + | The interrupt vector for timer 1 A is '''TIMER1_COMPA_vect'''. | ||
| + | |||
| + | ==Example== | ||
| + | |||
| + | <source lang="c"> | ||
| + | int | ||
| + | main(void) | ||
| + | { | ||
| + | ioinit(); | ||
| + | |||
| + | OCR1A = 499; | ||
| + | |||
| + | // Set up timer, prescaler = 8 (CS) | ||
| + | // and set the timer in CTC mode (WGM) | ||
| + | TCCR1B |= _BV(CS11) | _BV(WGM12); | ||
| + | |||
| + | // enable the timer interrupt | ||
| + | TIMSK |= _BV(OCIE1A); | ||
| + | |||
| + | // enable interrupts in general | ||
| + | sei(); | ||
| + | |||
| + | // do other stuff... | ||
| + | |||
| + | return 0; | ||
| + | } | ||
| + | |||
| + | ISR( TIMER1_COMPA_vect) | ||
| + | { | ||
| + | // do stuff | ||
| + | } | ||
| + | |||
| + | </source> | ||
Revision as of 23:45, 30 November 2009
Summary "howto" setup timer interrupts on AVR
Registers
- TCNTx
- is the timer counter itself. It's both readable and writeable. The counter starts as soon as prescale value is written to the CSxn (e.g. CS10 and CS11) bits, which are located in TCCRxB.
- OCRxA
- (output compare register). As soon as the timer reaches a value that is in this register, the appropriate bit in TIFR is set. This bit is set if the timer runs in CTC-mode, which can be switched on by setting WGMx0-WGMx3 to 0100 (setting WGMx2 to 1).
- TIMSK; Set the appropriate bit (OCIExA) to enable timer interrupts.
Interrupt vector
The interrupt vector for timer 1 A is TIMER1_COMPA_vect.
Example
<source lang="c"> int main(void) {
ioinit();
OCR1A = 499;
// Set up timer, prescaler = 8 (CS) // and set the timer in CTC mode (WGM) TCCR1B |= _BV(CS11) | _BV(WGM12);
// enable the timer interrupt TIMSK |= _BV(OCIE1A);
// enable interrupts in general sei();
// do other stuff...
return 0;
}
ISR( TIMER1_COMPA_vect) {
// do stuff
}
</source>