Difference between revisions of "AVR timer interrupts"

Revision as of 23:34, 30 November 2009

Summary "howto" setup timer interrupts on AVR

TCNTx: is the timer counter itself. It's both readable and writeable. The counter starts as soon as prescale value is written to the CSxn (e.g. CS10 and CS11) bits, which are located in TCCRxB.

OCRxA: (output compare register). As soon as the timer reaches a value that is in this register, the appropriate bit in TIFR is set. This bit is only set if the timer runs in CTC-mode, which can be switched on by setting WGMx0-WGMx3 to 0100 (setting WGMx2 to 1).

Revision as of 23:11, 30 November 2009 (view source) Danny (talk \| contribs) (Created page with 'Summary "howto" setup timer interrupts on AVR ==Registers== ;TCNTx: is the timer counter itself. It's both readable and writeable. The counter starts as soon as prescale value i…')		Revision as of 23:34, 30 November 2009 (view source) Danny (talk \| contribs) m Newer edit →
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	;TCNTx: is the timer counter itself. It's both readable and writeable. The counter starts as soon as prescale value is written to the '''CSxn''' (e.g. CS10 and CS11) bits, which are located in TCCRxB.		;TCNTx: is the timer counter itself. It's both readable and writeable. The counter starts as soon as prescale value is written to the '''CSxn''' (e.g. CS10 and CS11) bits, which are located in TCCRxB.

−	;OCRxA ~~and OCRxB~~: (output compare ~~registers~~). As soon as the timer reaches a value that is in ~~one of these registers~~, the appropriate bit in [[#TIFR\|TIFR]] is set. This bit is only set if the timer runs in ''CTC''-mode, which can be switched on by setting WGMx0-WGMx3 to '''0100''' (setting WGMx2 to 1).	+	;OCRxA: (output compare register). As soon as the timer reaches a value that is in this register, the appropriate bit in [[#TIFR\|TIFR]] is set. This bit is only set if the timer runs in ''CTC''-mode, which can be switched on by setting WGMx0-WGMx3 to '''0100''' (setting WGMx2 to 1).